Meeting minutes

July 22, 2013

 
Updates:
  • Optimized the 6-AIC along with its output crossbars.
  • The delay of the 6-LUT in 40nm is around 25% the delay of the same LUT in 130nm.
  • Designing sparse crossbars introduced minimal area reduction for both AICs and LUTs.
  • Preliminary results on the 4-LUT comparison (using the VPR mux in both VPR and Comet architecture delays).
  • The wiki is created and available for everyone to share information and results.
 
Future tasks/plans:
  • Stratix architecture: (Jerome)
    • Optimize the ALM design.
    • Implement the cluster crossbar.
    • Update the architecture according the Stratix IV specifications.
  • AIC architecture: (Rachel)
    • Implement the input crossbar
    • Simulate the design and report delay values.
  • Run experiments on Passkey using the VPR benchmarks. (John)
  • Figure out the reasons behind the difference in switch delays between VPR & Comet (& understand the delay model used in the architecture file). (Grace)
  • Tackle the sequential problem in VPR. (Grace)

July 15, 2013

 

Updates:
  • Scaled both the AIC and LUT clusters to the 40 nm technology.
  • The combinatorial AIC delay is around 400 ps (using the 40 nm).
  • We will be using Stratix IV as the reference architecture.
 
Future tasks:
  • Finalize the LUT-based cluster of the Stratix IV (Jerome).
  • Finalize the AIC-based cluster (Rachel).
  • Run experiments on Passkey and report delays (along with usage statistics) for a comparison with the delays generated using VPR (Colin).
  • Finalize the 4-LUT comparison and include the delays generated using Passkey (Grace).
  • Document the input crossbar designs for both the AIC and LUT clusters (Grace).
 
Extras:
  • Create a wiki to share data (David).

 

July 8, 2013

 

Updates:
  • The simulation of a 6-LUT showed on average a 1.5x increase in delay, i.e. 6-LUT delay = 1.5x 4-LUT delay (front end simulation).
  • Designing the AIC inversions using XOR gates instead of Inverter+Mux revealed to me more expensive both in terms of area and delay (about 8.5% increase in AIC combinatorial path delay).
 
Future tasks:
  • Share and discuss the input crossbar of a LUT based architecture (Grace).
  • Try to move from 130nm to 40nm technology (Rachel & Jerome).
  • Identify architectural differences between Stratix II/ III and Stratix IV, in order to have the reference architecture in the same technology node (Grace).
  • Run simulations on the AIC cluster and generate delay values, with a complete delay breakdown of the different components and paths in the cluster (Rachel).
  • Run some benchmarks on the IECAS tool flow, for the Comet architecture, and report delay values (logic, net and critical path delay) for a comparison with the values generated using VPR.

 

July 1, 2013

 

4-LUT comparison:
  • Provide the missing parameters to finalize the architecture file (Jerome--done).
  • Verify all inconsistencies & ambiguities in the data provided by the VPR people (Grace).
  • Run experiments and generate data for comparison (Grace).
 
6-AIC:
  • Investigate the efficiency tradeoffs when using XOR vs. multiplexer+inverter to provide the programmable output inversions of the AIC nodes (Rachel).
 
Stratix 6-LUT cluster:
  • Run some simulations on the 6-LUT to get delay measurements for a preliminary comparison with the 6-AIC (Jerome).
  • Design a sparse crossbar for the Stratix cluster, while keeping the full flexibility of the LUTs (Grace).