CAVA interrupt handling

The following diagrams shows how normal execution is interrupted when an interrupt arises.

When the control logic of the processor is aware that there is an interrupt the execution of the applications is interrupted. There are three cases where the processor can receive an interrupt:

• IRQ_REQUEST line of the processor is set
• Execution of an intruction to switch to kernel mode
• Execution of an intruction that generates a trap (e.g., division by 0, overflow, ...)

When the control logic of the processors realizes that any of these three cases are hapenning, the processor saves the next instruction to be executed in the Exception Program Counter (EPC) register. This allows the processors to return to the applications once the interrupt is handled. Then, the processor jumps to a section of the kernel code that handles the interrupts. The address where the program counter has to jump is specified in the Interrupt Polling Entry (IPE), which is specified at boot time. This kernel-code section is responsible of saving the program context, disabling interrupts (IRQs), jumping to the appropiate interrupt handler, enabling interrupts and restoring the context. When all of these tasks are futfilled, the program counter jumps to the address specified by the EPC, and the normal applications restores its execution normaly.