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Academic Infrastructure for EDA

Goals

The overall objective is to create a working flow from a Hardware Description Language (such as VHDL or Verilog) to a description of a mask set that can be fabricated. There are two main uses of such a flow:

Allow students to create chip designs, which can be fabricated by foundries such as MOSIS.

Allow students to do reseach on EDA. This often requires access to pieces of the flow which are different from the research interests. For example, a student working on timing driven placement needs a timer to evaluate the quality of their placement, and may need to modify the timer to work well with their application. However, writing a timer is a major job in itself, and the alternative of using a commercial timer means it cannot be modified (or even inspected in detail to see why it does what it does.) If an open-source timer is available, it makes research on timing driven algorithms much easier.

The flow

These are the pieces that are needed, along with some examples of what is already available. Eventually, we would like researchers to be able to mix and match among the available pieces.

Logic Synthesis: ??

Placement: CAPO,

Global Route: MaizeRouter, Fairly Good Router, Box Router

Detailed Route: None so far...

Extraction: OA Gear

Delay calculation: OA Gear

Timing analysis: OA Gear

Additional pieces that would be nice:

Logic Simulation

Formal Verification

Detailed extraction

Status:

Most of the pieces are available. What is needed is:

An open-source detailed router

Work to make a flow connecting all these tools possible

Strategy

How can we get this completed? So far we have worked with conferences, trying to coordinate their already existing contests, and adding our own funding to make the contests more attractive. Typically we provide additional prize money, which is available to the winners provide they make their code available to academic researchers. This worked well, for example, for the Global Routing contest at ISPD. There are now 4 available global routers, each better then the ones unvieled at the first contest.

However, there are limitations to working with conferences to establish the desired flow. First and most obvious, they may not be interested in holding a contest in the same area we would prefer. Second, most of the conferences are fairly specialized, and not responsible for the flow as a whole, generally just point tools within the flow.

So at some point, CEDA will need to explicitly sponsor some development. This can take two forms. One is a research project - for example creating a new detailed router that can create legal designs according to state of the art rules. The other is a purely software engineering effort to make sure the flow works - that each portion produces output files that can be fed to the next program in the flow.