//////////////////////////////////////////////////// // Owner: austriamicrosystems AG // // Business Unit Silicon Foundry // //================================================// // HIT-Kit: Digital // //////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////// // //============================================================================ TITLE "DRC/LVS 0.35 U 50V CMOS H35B4/H35B3 Last modified : 3-May-2005 " //============================================================================ // //===================================================================== // Version Date by Description //--------------------------------------------------------------------- // 1.0 22-Jul-2004 aob Basic version for HITKIT 3.61 // 23-Jul-2004 aob pmoshs/nmoshs poly corner checks improved // 26-Jul-2004 aob dnr002 improved, check for closed pdiff in rptub // 28-Jul-2004 aob nmos50hs x13 fixed for min w, rdiffnr corn corr fixed // 29-Jul-2004 aob small changes element rules // 10-Sep-2004 aob group shorted pads added, remove fill pattern ERC errs // 29-Sep-2004 aob module switches added // 12-Oct-2004 aob check for max dptub size , leak check modified // 19-Oct-2004 aob remove 2.5 x 5 U rects from thick met // 28-Oct-2004 aob replace rppinch by pjfet( extract, device, elements) // 2-Nov-2004 aob pjfet changed // 4-Nov-2004 aob iso width and iso ovlp pdiff only checked near device // 5-Nov-2004 aob w1rpnwsn check improved // 15-Nov-2004 aob nwell below rpoly2/cpoly fixed // 3.0 10-Dec-2004 aob doc rev 3.0 implemented // 22-Dec-2004 aob ill floating gate nmosi20 fixed // 14-Jan-2005 aob miss_ntap_dntub ... rule name fixed, gnd001 modified // 28-Jan-2005 aob leak check improved, duplicate text check added // 3-Feb-2005 aob leak check update // 21-Feb-2005 aob leak check update // 16-Mar-2005 aob parasitic update( xrc dummy statements) , met1/diffcon res // 22-Mar-2005 aob h35b3kc added // 11-Apr-2005 aob nmosfi25 added // 29-Apr-2005 aob dnr003/dnr004 improved for nested rptub // preliminary new checks for dist dntub/rptub ring // 2-May-2005 aob dnr003 : check dist 5.0 U to is (info only) // group coverage fixed ( met4) //--------------------------------------------------------------------- // //////////////////////////////////////////////////////////////////////////////////// // #DEFINE leakcheck //#UNDEFINE leakcheck // // ATTENTION : flag for definition of processes // // use h35b4 4 metal process //-------------------------- // #DEFINE fourmetal // global switch // // use h35b3 3 metal process //-------------------------- // //#UNDEFINE fourmetal // // use relaxed h35 rules for converted csx layouts //-------------------------------------------------- // //#DEFINE csxswitch // // do not use relaxed h35 rules for converted csx layouts //-------------------------------------------------------- // #UNDEFINE csxswitch /////////////////////////////////////////////////////////////////////// // // detailed process definition( module check) // /////////////////////////////////////////////////////////////////////// // // this section allows to select a more detailed processe( with/without // poly2, hres, midox ..). See DRC document for definitions // // If "process_switch" is not used, all modules are checked, only met3/met4 // is can be selected by "fourmetal" switch // // module check flags unsupported layers as DRC errors // module check disables unsupported devices in LVS // // select one process //--------------------- // // Attention for ntub/ptub devices are not flagges as errors //#DEFINE process_H35B3KC // core, pipcap, , 20Volt hres //#DEFINE process_H35A2IA // core, //#DEFINE process_H35A3I0 // core, ntub //#DEFINE process_H35B3A2 // core, pipcap, 20Volt ntub //#DEFINE process_H35B3B2 // core, pipcap, 5volt , 20Volt ptub , ntub //#DEFINE process_H35B4D3 // core, pipcap, 5volt , 20Volt, tmet4, ptub , ntub, hres // // dummy square for process DRC output // bound_cent = EXTENTS substrate_all CENTERS 1.0 // // default setting is check for all layers //----------------------------------------- // #DEFINE module_ptub #DEFINE layer_ntub #DEFINE layer_poly2 #DEFINE layer_midox #DEFINE layer_hres #DEFINE layer_metcap #UNDEFINE process_found_flag // // // set layers for processes //------------------------- // // H35A2IA // #IFDEF process_H35A2IA #UNDEFINE module_ptub #UNDEFINE layer_ntub #UNDEFINE layer_poly2 #UNDEFINE layer_midox #UNDEFINE layer_hres #UNDEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35A2IA { @ INFO : DRC checked with H35A2IA FLATTEN bound_cent } #ENDIF // // H35A3I0 // #IFDEF process_H35A3I0 #UNDEFINE module_ptub #DEFINE layer_ntub #UNDEFINE layer_poly2 #UNDEFINE layer_midox #UNDEFINE layer_hres #UNDEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35A3I0 { @ INFO : DRC checked with H35A3I0 FLATTEN bound_cent } #ENDIF // // H35B3A2 // #IFDEF process_H35B3A2 #DEFINE module_ptub #DEFINE layer_ntub #DEFINE layer_poly2 #UNDEFINE layer_midox #UNDEFINE layer_hres #UNDEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35B3A2 { @ INFO : DRC checked with H35B3A2 FLATTEN bound_cent } #ENDIF // // H35B3B2 // #IFDEF process_H35B3B2 #DEFINE module_ptub #DEFINE layer_ntub #DEFINE layer_poly2 #DEFINE layer_midox #UNDEFINE layer_hres #UNDEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35B3B2 { @ INFO : DRC checked with H35B3B2 FLATTEN bound_cent } #ENDIF // // H35B4D3 // #IFDEF process_H35B4D3 #DEFINE module_ptub #DEFINE layer_ntub #DEFINE layer_poly2 #DEFINE layer_midox #DEFINE layer_hres #DEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35B4D3 { @ INFO : DRC checked with H35B4D3 FLATTEN bound_cent } #ENDIF // // H35B3KC // #IFDEF process_H35B3KC #UNDEFINE module_ptub #UNDEFINE layer_ntub #DEFINE layer_poly2 #UNDEFINE layer_midox #DEFINE layer_hres #UNDEFINE fourmetal #UNDEFINE layer_metcap #DEFINE process_found_flag INFO_PROCESS_H35B3KC { @ INFO : DRC checked with H35B3KC FLATTEN bound_cent } #ENDIF //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // // do standard met3/met4 check if not set //----------------------------------------- // #IFNDEF process_found_flag #IFDEF fourmetal INFO_PROCESS_H35B4 { @ INFO : DRC checked with b35d4 ( 4 metal all modules) FLATTEN bound_cent } #ELSE INFO_PROCESS_H35B3 { @ INFO : DRC checked with h35b3 ( 3 metal all modules) FLATTEN bound_cent } #ENDIF #ENDIF // // output of unsupported layer for modules //------------------------------------------- // #IFNDEF layer_ntub ILL_NTUB_UNAVAILABLE { @ Process Modules : NTUB not available COPY NTUB } #ENDIF #IFNDEF layer_hres ILL_HRES_UNAVAILABLE { @ Process Modules : HRES not available COPY HRES } #ENDIF #IFNDEF layer_poly2 ILL_POLY2_UNAVAILABLE { @ Process Modules : POLY2 not available COPY POLY2 } #ENDIF #IFNDEF layer_midox ILL_MIDOX_UNAVAILABLE { @ Process Modules : MIDOX not available COPY MIDOX } #ENDIF #IFNDEF fourmetal ILL_MET4_UNAVAILABLE { @ Process Modules : MET4 not available COPY MET4 } ILL_VIA3_UNAVAILABLE { @ Process Modules : VIA3 not available COPY VIA3 } #ENDIF #IFDEF process_H35B3KC // // any gate outside dntub not allowed for this process // nmos50 also not allowed // ILL_TRANS_OUTSIDE_DNTUB { @ ERROR : gate outside DNTUB not allowed for this process H35B3KC (POLY1 AND DIFF) NOT DNTUB } #ENDIF // //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // INCLUDE "drc.ctrl" // // //