BottomUp Design

Introduction

This document contains most of the small details used while designing the LASP sensor chip at EPFL. I hope this information will be useful. All the illustrations and examples are taken from the LASP design. They should be general enough to be applied to other designs. Probably I forgot to mention many details.

Setup

The environment setup described here is specific to EPFL. At the moment of this writing here is my .cshrc:

---------- .cshrc ----------
source /softs/site/pre_cshrc -n
set amshk = v3.70
set cadence_ic = 5.0.33
set synopsys_dc = 2005.09
set modelsim = v6.1b
set cadence_soce = 4.1
set mentor_calibre = 2005.1
source /softs/site/post_cshrc
---------- .cshrc ----------

The design was made on AMS h35b4d3 technology.

TopDown

In a bottom-up design flow, the design is split into separate block which are implemented separately in top-down fashion. I recommend following Alain Vachoux's document on top-down design. I followed the directory structure and scripting described there. Note also you must think of the top-level design when design the blocks. Especially when doing place and route (P&R), you must place pins to facilitate routing but also think about power distribution.

Putting all together

Once all your blocks have been P&R, you can start the design of the top-level. The flow is very similar to a top-down flow. I present here some random piece of information to be take care of during this process. Keep in mind that the rest of the discussion is focused on the top-level and might not apply to low-level blocks.

Synthesis

In Synopsys you have the choice to make the tools see your blocks as blackboxes and/or inform it of their timing. I choose to inform the synthetizer about the subdesigns. To do so you need to do the following:

do not uniquify the design
add SYN/DB to the library search path in the .synopsys_dc.setup
in this same dir create symbolic links to your subdesigns. For eg if your subdesign is "myblock", you would have myblock_mapped.ddc in the DB directory. Then just do:

> ln -s myblock_mapped.ddc myblock.ddc

In this way Synopsys will see the timing of your subdesigns.

You need also to use the "propagate_constraints" command.

If you have "generic" for which you input '0' or '1' values, you have two choices. Either you let synopsys map the '0' and '1' to a tie_hi or tie_low cell or you can force them to remain '0' and '1' and take care of them in the place and route which can be configure to connect them to ground and vdd respectively. In the first case you don't have to do anything. In the latter, you must set a dont_touch on the _logic_0 and _logic_1 entities. In encounter you must use the globalNetConnect described below.

P&R

Pads

In my design I have separated the design core from the pads and synthetized the top_level (contained core and pads instance blocks, note this is hierachical design in encounter). The pads instance file being written in vhdl, doesn't contain gnd! or vdd! net. Therefore the core power pads nor the IO power pads are not instantiated there. To insert pads you can use the IO placement file (which will also place existing pads). Here is an example:

==================== IO file example ====================
Version: 2

### WEST SIDE ###
Orient: R270
Offset: 340.4000
Pad: IO_GND_0 W GND3OP                <= power pad instantiated and placed
Skip: 0.0000
Pad: IO_GND_0B W GND3OP
Skip: 0.0000
Pad: PADS/BLOCKOUT1 W                 <= regular pad placed
Skip: 0.0000
Pad: PADS/BLOCKOUT0 W
Skip: 0.0000
Pad: C_GND_0 W GND3RP
Skip: 0.0000
Pad: C_VDD_0 W VDD3RP
Skip: 0.0000
Pad: PADS/TCKPAD W
Skip: 0.0000
Pad: PADS/TMSPAD W

Pad: CORNERSW SW CORNERP              <= corner instantiated and placed

### SOUTH SIDE ###
Orient: R0
Offset: 340.4000
Skip: 0.0000
Pad: IO_VDD_0 S VDD3OP
Skip: 0.0000
Pad: PADS/VALIDPAD_0 S
Skip: 0.0000
Pad: PADS/DATAPAD_0_0 S
Skip: 0.0000
Pad: PADS/DATAPAD_0_1 S
...
===========================================================

Power Pads

SRoute can route the power nets to the power pads inserted like the example above. To do so you need to tell encounter to connect the pads pins the corresponding global net. Here is how I did it:

globalNetConnect gnd! -type pgpin -pin A -inst C_GND_* -module {} -verbose
globalNetConnect vdd! -type pgpin -pin A -inst C_VDD_* -module {} -verbose

note that in my case all the instances of core power pads where named C_GND/VDD_* and for this library the pad had a pin named A. Also you
need to have defined previously the global net (normally done in Vachoux's top-bottom design example):

globalNetConnect vdd! -type pgpin -pin vdd! -inst * -module {} -verbose
globalNetConnect gnd! -type pgpin -pin gnd! -inst * -module {} -verbose

TieHi/Lo

When your design contains '0' and '1' logic value to your blocks you might want the router to connect to the power ring/stripes. You do so yet again with the globalNetConnect command.

globalNetConnect vdd! -type tiehi
globalNetConnect gnd! -type tielo

Routing with Nanoroute

I route my design with nanoroute. You might succeed in using wroute but i got stuck with wroute because it doesn't accept blackbox in the design. Also if wroute inserts antenna diodes I didn't find a way to import these.

Finally, nanoroute might try to route all the signals in routing channels you don't want it to. To prevent it use routing blockages.

Note on wroute: use it on SUN for best results. Saw differences in clock route results especially on process antenna.

Process antennas

Process antennas can occur especially when you have long wire lines. The problem also arises when you have a hierarchical design and you don't specify the ANTENNAGATEAREA for all the blocks' pin. Ideally you would extract these values from each design directly from encounter and export it at the same time you do a lefOut. I didn't find a way to extract this information and I resorted to manually modify all the lef files. Here is what you should add for each pin:

PIN n_reset
    DIRECTION INPUT ;
    USE SIGNAL ;
    ANTENNAGATEAREA 0.5 LAYER MET2 ;             <= add this
    PORT
      LAYER MET2 ;
      RECT 3172.8000 0.0000 3173.4000 0.6000 ;
    END
END n_reset

You'll have to play with the values.

DRC/LVS

DRC and LVS where run with Mentor Calibre. You might also use Cadence Assura.

GDS

The gds exported from encounter doesn't contain the physical cells. To have a physical gds, I imported Encounter's gds in a Virtuoso's
library where I previously copies all the cells backends from AMS. Then exported the GDS. Note that you can do the import/export on the command line with the "pipo" command. To do so you also need to pass pipo a config file as argument

[strmin example]
> pipo strmin streamIn.il
[strmin config file]
===streamIn.il===
streamInKeys = list(nil
        'runDir                 "."
        'inFile                 "/home/cfavi/projects/lasp2/sandbox/lasp2/PAR/DEX/mux.gds"
        'primaryCell            "mux"
        'libName                "FULLLIB"
        'techfileName           ""
        'scale                  0.001000
        'units                  "micron"
        'errFile                "./DRC/mux/streamIn.log"
        'refLib                 nil
        'hierDepth              20
        'maxVertices            1024
        'checkPolygon           t
        'snapToGrid             nil
        'arrayToSimMosaic       t
        'caseSensitivity        "preserve"
        'zeroPathToLine         "lines"
        'convertNode            "ignore"
        'keepPcell      nil
        'skipUndefinedLPP       t
        'ignoreBox              nil
        'mergeUndefPurposToDrawing              nil
        'reportPrecision        nil
        'keepStreamCells                nil
        'attachTechfileOfLib            ""
        'runQuiet               nil
        'noWriteExistCell               t
        'NOUnmappingLayerWarning                nil
        'genListHier            nil
        'cellMapTable           ""
        'layerTable             "/softs/dkits/ams/v3.70/artist/HK_H35/TECH_H35B4/strmInOut.layertable"
        'textFontTable          ""
        'restorePin             0
        'propMapTable           ""
        'propSeparator          ","
        'userSkillFile          "/softs/dkits/ams/v3.70/artist/HK_H35/skill/ams_sdl.il"
        'rodDir                 ""
        'refLibOrder                    ""
)
=================
[strmout example]
> pipo strmout streamOut.il
[strmout config file]
===streamOut.il===
streamOutKeys = list(nil
        'runDir                 "."
        'libName                "FULLLIB"
        'primaryCell            "mux"
        'viewName               "layout"
        'outFile                "./DRC/mux/mux.gds"
        'scale                  0.001000
        'units                  "micron"
        'compression            "none"
        'hierDepth              20
        'convertToGeo           nil
        'maxVertices            200
        'refLib                 nil
        'libVersion             "3.0"
        'checkPolygon           nil
        'snapToGrid             nil
        'simMosaicToArray       t
        'caseSensitivity        "preserve"
        'lineToZeroPath         "path"
        'convertDot     "ignore"
        'rectToBox              nil
        'convertPathToPoly      nil
        'keepPcell      nil
        'useParentXYforText     nil
        'reportPrecision        nil
        'runQuiet               nil
        'errFile                "./DRC/mux/streamOut.log"
        'NOUnmappingLayerWarning                nil
        'techFileChoice         nil
        'pcellSuffix            "DbId"
        'respectGDSIILimits             nil
        'dumpPcellInfo          nil
        'genListHier            nil
        'cellMapTable           ""
        'layerTable             "/softs/dkits/ams/v3.70/artist/HK_H35/TECH_H35B4/strmInOut.layertable"
        'textFontTable          ""
        'convertPin             "geometry"
        'pinInfo                0
        'pinTextMapTable        ""
        'propMapTable           ""
        'propSeparator          ","
        'userSkillFile          "/softs/dkits/ams/v3.70/artist/HK_H35/skill/ams_sdl.il"
        'rodDir                 ""
)
==================

DRC / Antennas

Once you have a "physical" GDS, you can run DRC. You need several configuration files for it:

AMS process rules file. Found in AMS HK distribution.
DRC Configuration. Some example can be found in Calibre directories. M. Sergio split the standard configuration in two files from Calibre so that it is more manageable. The drc.ctrl contains the reference to your gds and main options (edit this one). The drc_header contains all the rest.

You run calibre either with a gui (try calibre -gui) or from the command line:

> calibre -drc -hier -turbo -turbo_all drc_rule_file

Note that you can import Calibre result file directly in Encounter. You just have to go to the Verify menu.

LVS

You might need to modify the layout to match lvs. I had to do the following in Virtuoso:

shortcut power rings
add power labels on layer ????METX PIN???? and then created the pins with the command "create pins from labels"

You also need to import the Verilog from Encounter into Cadence library to be able to generate a CDL. Before you do the verilogIn you need to manually edit the file.

remove gnd! vdd! to all blocks definition and instance including pads
remove all fillers but not the FILLANT blocks
remove all pad corners
if you had '0' or '1' assignement in blocks replace those with 1'b0 and 1'b1

You either import the vhdl from Cadence library system or from the command line.
Importing a verilog file:
> ihdl -param paramfile verilog_file.v
Exporting a CDL:
> si $DIR -batch -command netlist
where $DIR is a directory containing the si.env configuration file.

Annexes

Synthesis script

P&R scripts