Characterization and Modeling of nanoscale MOSFET for RF design

C.C. Enz, J.-M. Sallese, A. Mangla

Introduction

The quest for tera-bits per second speed and larger packing density for digital circuits have led to an unprecedented scaling of CMOS, the workhorse of the semiconductor industry, 50 nm feature size today and and heading towards 10-20 nm in the next few years. The aggressive CMOS technology scaling has also increased the transit frequency $latex f_t$ and the maximum frequency of oscillation $latex f_{max}$ to record values (425 GHz $latex f_t$ and 400 GHz $latex f_{max}$ for a 45 nm bulk CMOS process). This has opened the door to the integration of complete RF transceivers for millimeter-wave applications, on a single chip.

However, for an increasing number of applications low power consumption is a more critical issue than high speed operation. Stringent power budgets have spawned the rapid growth of advanced low-power digital design, of which subthreshold design, in which the supply voltage is scaled below the device threshold voltage, has emerged at the forefront. Similarly, many wireless applications remain in the GHz frequency range and therefore do not need 425 GHz peak $latex f_t$. The RF transistors’ $latex f_t$ can hence be reduced to the minimum required by the application by shifting the transistors bias point from strong inversion towards weak inversion, which basically corresponds to trading speed with current consumption.

Although a lot of effort has already been invested in subthreshold digital circuit design and mm-wave RF circuits, very little or even nothing has been published today in the field of using nanoscale MOS transistors in deep weak inversion for ultralow-power analog and RF circuits. There is therefore a potentially unexplored area of using deeply scaled CMOS processes for RF applications in the GHz frequency range, where the operation of the MOSFET in deep weak inversion would be possible and may result in significant power savings. Moreover, the degradation effects like parameter variability, stronger short-channel effects higher leakage currents and other novel degradation mechanisms which were not present in older technologies, would have a significant impact on the operation and the analog and RF performance of the device, particularly in the region of weak inversion. It is now time to reinvestigate the performance and limitations of nanoscale MOSFETs biased in weak inversion in the perspective of using them in complex SoCs.

The objectives of this project are:

• Fully characterize several nanoscale CMOS technologies (65 nm or 45 nm, depending on availability, and then 32 nm) for operation in weak inversion for analog and RF circuits. The characterization includes dc, small-signal, RF and noise parameters.
• Evaluate the behavior of existing compact models in weak inversion by comparing with measurements. Improve the models and derive a clear design methodology in order to be able to efficiently design analog and RF circuits operating in weak inversion and integrated in nanoscale technologies.
  
• Evaluate the improved compact models together with the design methodology through the design of simple but representative analog and RF building blocks.