Characterization and Modeling of nanoscale MOSFET for RF design

Analog & RF Circuits in Nanoscale CMOS

As already discussed, the technology scaling of the channel gate length $latex L_g$ has resulted in raw performance benefits, particularly in the speed of the transistor, that are mostly beneficial to digital circuits. But, a big penalty has been paid in other more analog type of performance metrics, in particular the device small-signal output conductance $latex g_{ds}$ which translates into low intrinsic gain ($latex A_v = g_m/g_{ds} ≅10$) and extremely low supply voltages strongly limiting the achievable dynamic range. In the RF regime, CMOS has proved viable as a low cost alternative to traditional SiGe and III-V semiconductor technologies and promises higher levels of integration and reduced cost. The move of CMOS to millimeter-wave applications in the 60 GHz ISM band and beyond is made possible by the phenomenal increase of the transit frequency $latex f_t$ and maximum frequency of oscillation $latex f_{max}$ resulting from the channel length scaling. Today, record peak $latex f_t$ and $latex f_{max}$ of up to 425 GHz and 400 GHz, respectively, have been reported for a 45 nm bulk CMOS process [22]. Even higher values of 485 GHz and 345 GHz of peak $latex f_t$ and $latex f_{max}$ are achieved for a 45 nm SOI CMOS technology [23]. High transit frequency usually results also in low minimum noise factor $latex F_{min}$ since the later is related to $latex f_t$ by [24]

$latex F_{min} \cong 1+2\frac{\omega}{\omega_t}\sqrt{\gamma_{nD}.\beta_{nG}.(1-c^2_g)}$     

where $latex \gamma_{nD}$ is the excess noise factor (typically around unity for long channel devices and increasing to about 2.5 for short channel devices [24]), $latex \beta_{nG}$ the gate-induced noise excess factor (about 0.2 for long channel devices [24]) and $latex c_g$ the correlation coefficient between the drain and gate induced noise (about 0.6 in weak inversion) [24][25][26]. Note that the noise factor is further degraded by the unavoidable shot noise related to the gate leakage current appearing in nanoscale devices. Since the latter is strongly increasing with the gate bias voltage, it might be that the impact of gate tunneling shot noise on the minimum noise factor $latex F_{min}$ will be lower in weak inversion.